That was before working out the full instruction encodings.  Earlier I added in a switchable bank of 10 memory-mapped registers to reduce the number of memory accesses required, but that is between tricky and impossible to map into the opcode space - and there's actually a better way to do it, that we can steal from the Z80.

When working through the CPU programming model I also added in a LEAF instruction - Load Effective Address, Fractional - explicitly for table interpolation.  With this new model our algorithm turns out somewhat different:

Instruction     Cycles  Comment

GRP 1           1       'Switch to register group 1
LEAF X, X+Y     2       'Calculate an effective address in interpolated mode

Oops, that's wrong.  Sorry about your burned-out speakers.  Let's try again.

Instruction     Cycles  Comment

BANK 1          1       'Switch to register group 1

ADD X, Y        1       'Increment the offset by the step size

AND X, Z        1       'Restrict the offset to the sample size

The trick we've stolen from the Z80 is just to have multiple sets of registers.  The Z80 had two register sets in 1976, we need five or six in 1983.  That doesn't seem too implausible.

The LEAF instruction replaces the complicated high/low byte address fiddling.  It only saves three cycles but it's a lot easier to read.  If you're reading through some Imagine assembler and you see LEAF, you immediately know it's doing some kind of table interpolation.  (And if you see LEAP, that's a jump table.  It's actually LEA P, but the assembler will accept LEAP.)

Update 2020-09-14

We no longer need to use the LEAF instruction explicitly; if you specify (W+XH) as the index mode in any instruction that can take indexing postbyte, it calculates the address in interpolated mode.

This version of to code removes the CMP / IF / CLR logic and goes with the method used in the Ensoniq 5503 as found in the Apple IIgs.  Sample banks are a fixed power-of-two length - 64, 128, 256, 512, or 1024 bytes - so we can simply AND the offset with a bit mask to clip it to the appropriate range.

One other thing: When I was first thinking of the custom chips for the Imagine I called this a fixed-function DSP, even though it was fully-programmable.  It just seemed like a good name.  Then I realised exactly why this version of the chip would be described as fixed-function.

It has a small - maybe 256 bytes - mask-programmed ROM containing a bunch of DSP algorithms, like the code above.  You can still write your own custom algorithms, but if you're running code out of the on-board ROM, and you have your settings loaded into the registers, we only need to access main memory three times per sample: Two reads to issue the subroutine call, and one when the subroutine loads the sample data.